Delivered versus roadmap

An explicit honesty boundary (ADR 0005): delivered capability is separated from roadmap, and unimplemented claims are gated rather than asserted. A named-device timing result is never inferred from an unrouted design.

Delivered today
✓Software kinematic, lifecycle, diagnostic, and AER surfaces.
✓Two-tier formal verification (Lean software invariants + SymbiYosys hardware proofs).
✓Bit-true Q8.8 SystemVerilog trigger and veto logic with Verilator cosimulation.
✓Formal cycle-budget bound (timing:cycle-budget-formal) and fault-injection cosimulation.
✓Multi-language acceleration chain with fastest-measured dispatch and pure-Python fallback.
Hardware-gated (not yet delivered)
⚠Vivado ZU3EG timing closure — timing:post-route-hardware-gated.
⚠The full P6 hardware trigger chain and measured end-to-end nanosecond latency — timing:e2e-hil-hardware-gated.
⚠Named-device post-route waveform equivalence against the physical rig.
Status

Pre-alpha

The software kinematic, lifecycle, diagnostic, formal, and AER surfaces are present; Vivado ZU3EG timing closure and the full P6 hardware trigger chain are not yet delivered capabilities. The delivered formal timing bound is expressed in clock cycles, not nanoseconds on a named device.