A network trained in clean floating-point and dropped onto an FPGA meets a harsher world: weights rounded to fixed point, comparators that differ neuron to neuron, a clock that jitters. Each imperfection nudges the behaviour, and together they can undo a model that looked perfect in simulation. SC-NeuroCore's answer is a digital twin — a model of the device's flaws that runs during training, so the network learns weights that already survive them. Compare the ideal and the twin below.
Four imperfections dominate a digital neuromorphic FPGA. Weights and states are stored in fixed point — a Q8.8 word rounds every value to a multiple of $2^{-8}$. Process variation perturbs each weight by a percent or two, and comparators give every neuron a slightly different threshold. The clock jitters, stretching and shrinking timesteps. The twin applies all four; the demo isolates the first two, which set the accuracy floor.
The grey line is the ideal identity mapping; the blue points are what the hardware twin returns after rounding each perturbed weight to the fixed-point grid. Drop from Q8.8 to Q4.4 and the grid coarsens visibly — the points snap to a ladder. Raise the variation and they scatter off the line. Training with the twin in the loop teaches the network to place its decision boundaries where this scatter cannot cross them, which is the difference between a model that works in simulation and one that works on silicon.
The twin models five imperfections, each from its measured character. Together they are calibrated against published data — roughly a 20% coefficient of variation for analog mixed-signal neuromorphic processors, and a much lower 1–5% for digital FPGAs, where fixed-point quantisation is the dominant error rather than device spread.
| Imperfection | Model | Default |
|---|---|---|
| Fixed-point quantisation | Q-format rounding to $2^{-f}$ | Q8.8 (16-bit) |
| Weight perturbation | multiplicative Gaussian, then quantise | CV = 2% |
| Threshold mismatch | per-neuron multiplicative Gaussian | CV = 5% |
| Clock jitter | per-step timing $\mathcal N(1,\sigma)$, clipped to $[0.9,1.1]$ | 1% |
| Routing skew | path-dependent timing offset | modelled |
The digital twin is the confidence step between training and tape-out. Whatever produced the network — surrogate gradients, local plasticity, conversion — the twin re-runs it against a faithful model of the target FPGA before a single bit is synthesised, so the gap between the simulated accuracy and the deployed accuracy is measured and closed in advance rather than discovered on the bench.
Evidence boundary: the demo runs the library's exact Q-format quantiser and multiplicative-Gaussian weight perturbation in your browser. The default coefficients of variation are calibrated-against-published-data estimates for the named device classes, not measurements on a specific board; a real deployment's mismatch depends on the fabric and the design. No accuracy-retention figures are quoted.