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NIR & interoperability
compile the standard to silicon

The neuromorphic world finally has a lingua franca: the Neuromorphic Intermediate Representation, a framework-agnostic graph that every major spiking-network library can export. SC-NeuroCore's distinctive move is to compile a supported NIR graph straight to synthesisable Verilog — so a model trained anywhere can be deployed to an FPGA, without rewriting the network by hand.

Train anywhere, deploy to silicon

Pick the framework you train in. Its NIR export is the same graph SC-NeuroCore's compiler consumes, so the path to hardware is the same regardless of where the model came from.

snnTorchfloat32 training
NIR graph18 primitives
NeuronGraphquantise Q8.8
Verilog RTLgenerated
FPGAdeployed

Support is for NIR graphs the compiler covers — the primitives and topologies it maps — not every conceivable graph; unsupported nodes are reported rather than silently dropped.

01  NIR — the universal exchange format

NIR defines a spiking network as a directed graph of about eighteen primitives — neurons, affine maps, connections — independent of any one framework. Because the major libraries all export to it, a single importer that understands NIR understands them all. It is the neuromorphic analogue of ONNX for deep learning.

Deeper: mapping primitives to equations
SC-NeuroCore maps the NIR neuron primitives onto its canonical ODE-string representation — the same equation form the rest of the compiler uses — and preserves NIR's affine (weight-and-bias) semantics exactly, so the imported network computes what it did in training. One-step recurrent feedback is kept explicit with a delay_steps annotation rather than being flattened away, so recurrent architectures survive the trip to hardware.
02  One command to Verilog

The pipeline is a single flow: import the model into a graph, extract the topology, quantise the parameters to fixed-point, generate a neuron module per node, and emit synthesisable RTL — the same bit-true hardware path the rest of the toolkit uses, so the deployed circuit is provably the imported network.

03  Framework reach

Train in whatever suits the problem — snnTorch, Norse, Rockpool, Sinabs — in float32, then export NIR and deploy. For models that live in the deep-learning world, an ONNX → NIR shim brings them into the same graph, and the round-trip is checked so what you deploy matches what you trained.

04  Beyond NIR

Interoperability does not stop at NIR. A NeuroML importer brings in computational-neuroscience models, a SpikeInterface path ingests recorded neural data, and PyTorch/JAX bridges connect the training ecosystems — so SC-NeuroCore sits at a crossroads rather than in a silo.

Where it fits

NIR is what makes SC-NeuroCore a deployment target rather than another island: it does not ask you to abandon your training stack, only to export the graph everyone already agrees on — and then it does the one thing the other tools do not, which is turn that graph into silicon.