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Security & sovereignty
provenance for the silicon supply chain

A neuromorphic design is not just an algorithm — it is a piece of hardware with a supply chain that can be tampered with, cloned, embargoed, or irradiated. SC-NeuroCore's compiler treats that as a first-class concern: it can lint for trojans, emit a software bill of materials, obfuscate and watermark the IP, schedule radiation scrubbing, and target export-free sovereign silicon — each with an explicit, honest evidence boundary.

01  Supply-chain integrity

Two design-time checks guard the front door. A hardware-trojan lint scans the compiled equations for dormant triggers and hidden payloads before synthesis; a software bill of materials (SBOM) records every dependency in CycloneDX or SPDX form — the artefact the EU Cyber Resilience Act will require for shipped devices.

Deeper: what the lint and SBOM produce
The trojan lint returns a structured result flagging dormant-trigger and payload patterns for review — it is a static design-time screen, not a proof of trojan-freedom. The SBOM is generated per module and profile with its dependency graph, in the standard machine-readable formats procurement and compliance tooling expect, so a shipped neuromorphic part carries the same supply-chain paper trail as any other regulated software artefact.
02  IP protection

Silicon IP is expensive and copyable. Logic-locking obfuscation makes a netlist unusable without a key, and constraint-based watermarking embeds a verifiable owner signature into the design — so a cloned or exfiltrated netlist can be both frustrated and attributed.

Deeper: locking and watermarking
Obfuscation inserts key-gated logic (a configurable key length) so that the circuit only computes correctly under the right key, raising the cost of unauthorised reuse. The watermark is woven into the design constraints rather than bolted on, so it survives synthesis and can later be recovered to demonstrate provenance in a dispute. Both are generated by the same compiler that emits the functional RTL, so they travel with the design rather than being a separate manual step.
03  Side-channel-aware encoding

A circuit can leak secrets through its power draw or timing. SC-NeuroCore can generate activity-balanced stochastic streams — deterministic and probability-preserving — plus optional dummy streams, so that switching activity carries less class-dependent structure. The visual below is an analytic illustration of that balancing.

Analytic illustration — switching activity, raw vs balanced
raw class-gap —  balanced class-gap —  (lower is flatter)

Honest boundary — analytic_simulation_only. This workflow reports design-time proxies only: per-stream transition counts and rates, class-conditioned activity, the baseline-versus-protected class-mean gap reduction, dummy-stream overhead, and the generated HDL-hook metadata. It provides no physical power or thermal measurement, no DPA-resistance claim, and no silicon-security claim. Board measurements, power-rail and oscilloscope traces, place-and-route timing and adversarial lab validation are separate evidence classes and must be recorded separately.

04  Harsh environments — space & chiplets

Beyond the lab, configuration memory flips under radiation and large designs span multiple dies. SC-NeuroCore can schedule single-event-upset scrubbing for a given orbit and shielding, and map a design across a UCIe chiplet interconnect — the plumbing that turns a neuromorphic core into a deployable part in a demanding environment.

Deeper: SEU scrubbing and UCIe mapping
The scrubbing scheduler takes an orbit altitude and shielding thickness and produces a refresh schedule for the configuration bits, so that upsets are corrected before they accumulate into a functional failure — the standard technique for FPGAs in space. The UCIe mapping partitions blocks across chiplet lanes at a chosen lane bandwidth and protocol version, letting a design exceed a single die's budget. Both are compiler outputs, so they stay consistent with the functional design.
05  Sovereignty — export-free targets

For teams that cannot depend on export-controlled parts, the compiler carries RISC-V sovereign-AI hardware profiles — an open instruction set with commercially available cores — so a design can target silicon that is free of ITAR/EAR entanglements, alongside emerging magnonic and organic-bioelectronic research profiles.

Deeper: the profile system
A hardware profile captures a target's resources and constraints so the same design can be retargeted without rewriting it; the sovereign set covers open RISC-V AI platforms, and there are additional research-tier profiles (magnonic spin-wave, organic bioelectronic) for teams exploring post-silicon substrates. Retargeting is a profile swap, and the readiness of each is stated rather than assumed — some are production-oriented, others explicitly experimental.
The hardware path →Industrial readiness →
What this is — and is not

These are design-time capabilities: they produce artefacts — lint results, SBOMs, watermarks, scrub schedules, activity reports — that make a security and sovereignty case reviewable. They are not a substitute for silicon-level security validation. A trojan lint is a screen, not a guarantee; an activity report is a proxy, not a power-analysis result; a sovereign profile is a target, not a certification. The value is an auditable trail with its boundaries stated, which is exactly the discipline the rest of the toolkit follows.

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