MIF Studio
Inspect merge-window admission, formal certificates and local RTL cosimulation with evidence that can be traced to its inputs.
SDK vertical and panel · Hub integration planned · Source review: 2026-09-26
What it is for
Inspect merge-window admission, formal certificates and local RTL cosimulation with evidence that can be traced to its inputs.
Who it is for
Researchers and hardware engineers validating magneto-inertial fusion timing and logic models.
Documented capabilities
- Evaluate a bounded merge-window and admission model.
- Generate or inspect formal proof certificates bound to a digest.
- Run local bit-exact Verilator cosimulation and benchmark with provenance; the contract exposes evaluate, prove, cosimulate and benchmark.
A typical workflow
Configure a bounded model → evaluate admission → inspect a formal certificate → cosimulate locally where supported → export benchmark and evidence records for review.
Scope and evidence
cosim:local-verilator is distinct from hil:hardware-gated. Local cosimulation proves neither FPGA hardware operation nor chamber safety. The panel's sample fallback is not a measured run.
Local setup and dependencies
Install the optional scpn-mif-core[studio] extra in the documented environment. Formal and Verilator workflows need their respective toolchains; follow the Studio vertical guide.
Availability and access
The Hub registry lists MIF as coming soon. Use the documented local workflow and project access terms; hardware-in-the-loop requires a separate authorised environment.
Read the project sources
Project overview · All Studios and their roles · Discuss a research or deployment workflow