Loop Timing Witness
Published host-analysis software and an architecture project for CPU/FPGA control-loop timing, energy and fault-response evidence. Hardware measurements are pending.
Hardware: architecture only. Software: published v0.1.0. This registered research project does not yet report hardware measurements.
What it is intended to do
LOOP-TIMING-WITNESS is intended to witness the timing of a complete control loop across CPU and FPGA placements. The planned evidence includes latency, jitter, energy and fault response, retained as raw records with hashes.
Who it is for
Researchers and engineers who need to distinguish a software timing model from measured end-to-end hardware behaviour.
The intended evidence workflow
Specify a loop and hardware placement → define measurement boundaries → capture raw timing and fault records → retain provenance and hashes → review what the measurements actually support. This workflow is an architectural goal, not a report of completed measurements.
Current evidence boundary
Board-platform facts are taken from documentation; verified_on_hardware is false. No latency, jitter, energy or physical fault-response performance claim is made. This project is separate from the implemented SNN Studio inside SC-NeuroCore.
Project sources and context
Project repository · Registered portfolio record · SNN Studio · All Studios
Package release reviewed 2 October 2026: PyPI 0.1.0 · software DOI. Physical board qualification remains pending.
Choose your first step
Analyse timing records on the host and inspect the published simulation and schema examples.
Read the installation guide or example · Discuss an integration
What you need
Use the published Python package and documented example records. Physical measurements additionally require the specified board and measurement setup.
How to interpret the result
Software v0.1.0 is published; hardware qualification remains architecture-only. Example or simulated records are not physical board measurements.