Loop Timing Witness

An architecture project for reproducible evidence of complete CPU and FPGA control-loop timing, energy and fault response. Hardware measurements are pending.

Architecture only. This registered research project does not yet report hardware measurements.

What it is intended to do

LOOP-TIMING-WITNESS is intended to witness the timing of a complete control loop across CPU and FPGA placements. The planned evidence includes latency, jitter, energy and fault response, retained as raw records with hashes.

Who it is for

Researchers and engineers who need to distinguish a software timing model from measured end-to-end hardware behaviour.

The intended evidence workflow

Specify a loop and hardware placement → define measurement boundaries → capture raw timing and fault records → retain provenance and hashes → review what the measurements actually support. This workflow is an architectural goal, not a report of completed measurements.

Current evidence boundary

Board-platform facts are taken from documentation; verified_on_hardware is false. No latency, jitter, energy or physical fault-response performance claim is made. This project is separate from the implemented SNN Studio inside SC-NeuroCore.

Project sources and context

Project repository · Registered portfolio record · SNN Studio · All Studios

Source review: 26 September 2026.