“This classification cost 4.2 nanojoules.” That is the sentence neuromorphic hardware is supposed to earn, and it is only honest if you can account for every picojoule. SC-NeuroCore tallies energy the way the chip spends it — per synaptic operation, per membrane update, per spike, per memory read, per routed event — against measured-class per-operation costs for real targets. The result exposes the core of the efficiency argument: synaptic energy scales with spikes, membrane updates scale with the clock.
Every inference decomposes into a handful of countable operations. A spike drives $N_{\text{in}}$ synaptic operations, each of which also reads a weight from memory; every neuron takes a membrane update on every timestep whether or not it fires; each spike costs a comparator-and-reset to generate and a hop to route. Multiply each count by its per-operation cost in picojoules and sum. The one asymmetry that matters is in the counts, not the costs.
Turn activity down and the synaptic and memory bars shrink with it — a spiking network only pays for the neurons that actually fire, which is the whole event-driven argument. But the green membrane-update bar does not move: every neuron is still clocked every timestep, so it is a fixed floor paid even at zero activity. That floor is exactly why event-driven hardware, which skips the update for silent neurons, matters — and why a sparse workload on a densely-clocked device leaves efficiency on the table. The “vs fully-dense” figure is what the same layer would cost if every neuron fired every step.
The calculator uses the toolkit's hardware cost model — per-operation energies, in picojoules, for each target. These are literature-class figures for the named devices, not measurements taken on this page; they set the relative economics, which is what the model is for.
| Target | SynOp (pJ) | Membrane (pJ) | Spike gen (pJ) | Mem read (pJ) | Routing (pJ) |
|---|---|---|---|---|---|
| Loihi 2 | 23.6 | 1.2 | 0.5 | 4.0 | 3.0 |
| Akida | 10.0 | 0.8 | 0.3 | 3.0 | 1.0 |
| Analog 28 nm | 1.6 | 0.2 | 0.1 | 0.5 | 0.3 |
| FPGA Artix-7 | 30.0 | 3.0 | 1.0 | 8.0 | 0.3 |
| FPGA iCE40 | 50.0 | 5.0 | 2.0 | 10.0 | 0.5 |
This is the operational-energy model behind the numbers used elsewhere on the site: the carbon page turns these picojoules into grams of CO₂ over a device's life; the hardware and compiler pages choose targets whose costs this table encodes. It is deliberately the same accounting the toolkit runs, so a claim made here can be traced to a count of operations rather than a slogan.
Evidence boundary: the calculator runs the library's exact accounting arithmetic in your browser on the per-operation cost table above. Those per-operation energies are literature-class figures for the named targets, not measurements on this page; a real deployment's energy depends on the mapping, the data, and the device. No wall-clock or throughput figures are quoted.