Every other page here shows one capability and lets you drive it. This one steps back to the question they all answer: why build on a stochastic substrate at all, what that choice actually buys and costs, how the pieces stack up, and — kept deliberately separate — how far the idea is aimed. It is written to the same rule as the rest of the portal: claims stay tied to what is built, and what is not yet built is labelled as such.
A conventional computer keeps memory and arithmetic in separate places and shuttles data between them for every operation. At the scale of large models and dense sensor networks, that shuttle — not the arithmetic — dominates the energy bill. Making the multiplier faster does not help when the cost is moving the operands. The interesting question is whether a different representation can make the common operations cheap enough that the movement stops mattering.
Stochastic computing answers with a deliberately strange representation: a number $x\in[0,1]$ is not a fixed-point word but a probabilistic bitstream — a sequence whose bits are one with probability $x$. Under that encoding the expensive operations collapse. Multiplication of two independent streams is a single AND gate; a scaled addition is a multiplexer. A single flipped bit is a small change in an estimate, not a corrupted value, so the scheme is intrinsically fault-tolerant — and it reads naturally as the rate-coding that biological neurons already use.
The bet is not free, and the honest half of it is the third term. A bitstream of length $N$ estimates its value only to about $1/\sqrt{N}$ — roughly three percent at a thousand bits — so stochastic computing is a trade, not a free lunch: it gives up bit precision to buy parallelism, energy and robustness. That makes it a strong fit for error-tolerant workloads — perception, inference, control under noise — and a poor one where every last bit must be exact. The whole library is an attempt to make that trade pay where it can, and to be plain about where it cannot. The mechanics, with a bitstream you can drive yourself, are on the stochastic computing page.
The framework is layered from the physics of a single neuron up to whole-system deployment. Each layer below is a real, working part of the library with a page that demonstrates it — the stack is a table of contents, not a promise.
The claim the layering makes is modest and testable: one representation carries all the way from a single neuron to a synthesised chip without changing underneath you. That is why a network trained with surrogate gradients, a rule learned locally, and a model converted from PyTorch can all be measured against the same energy model and the same device twin.
The portal covers a wide span, and not all of it is at the same maturity. The honest split is worth stating outright: the left column is demonstrated in code you can drive on these pages; the right column is genuine research direction — real modules in many cases, but not claims of a finished capability.
The project deliberately reasons past anything that could ship, and it is worth being honest that this is where the thinking goes rather than pretending it does not.
A representation that survives a bit flip and carries unchanged from a neuron to a chip invites a question about scale: how far up does the same substrate reach? The library keeps a few provocations at that edge — delay-tolerant networking for very long latencies, energy routing for very large harvesters — not as products or a plan, but as stress tests that ask whether the architecture is genuinely scale-invariant or merely looks it. They are labelled here as exactly that: open questions at the far end of a research programme, held apart from everything above, which is built and drivable today.
The engineering claims — the accelerated kernels, the bit-true hardware equivalence and their benchmark methodology — live in the released engine paper, with its own figures and its own context. It is linked here as the primary reference rather than restated, so the numbers stay attached to the method that produced them. Performance figures on this portal are kept on the pages that measure them honestly: the energy model and the benchmarks.
SC-NeuroCore is dual-licensed: AGPL-3.0-or-later for research and education, and commercial licences for proprietary integration. The concepts and the code are the author's own, tracked openly.
Evidence boundary: this page is a synthesis, not a source of new measurements. Every capability it calls demonstrated links to the page that runs it; everything else is marked research-tier or, in the far-horizon section, speculation. Performance numbers are deliberately kept off this page and left on the energy and benchmark pages, and in the released paper, where they carry their method. The licence and copyright shown match the library's source headers.